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JPS6167147A Expired / Lapsed JP ⏱️ 0.0 years remaining

Integrated circuit scan-in/scan-out method

Assignee: Hitachi Ltd
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Filing: 1984-09-10
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Granted: —
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Expires: 2004-09-10
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Abstract

Abstract PURPOSE:To improve the reliability and diagnostic performance by providing a scan register to an integrated circuit and storing a scan command address to the register so as to reduce number of pins of the integrated circuit applying scan-in/scan-out. CONSTITUTION:A terminal connected to scan-in interface signal lines 1-5 is provided to the integrated circuit for scan-in/scan-out system and a scan-in data SID from the signal line 1 is fed to a scan register 6. Further, a scan enable SE and a scan timing SIT2 from the signal lines 3, 4 are fed to a scan bit counter 7 and the enable SE is fed to a scan decoder 12. The scan address and control information inputted serially to the said circuit are set to the register 6 by the counter 7. Then a scan object FF15 uses a command of the register 6 so as to discriminate scan-in or scan-out, allowing to execute the scan-in or scan-out with less number of pins.

Inventors

  • 👤 Kiyoshi Yada
  • 👤 矢田 潔
  • 👤 Masao Kato
  • 👤 正男 加藤

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 17:09
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236

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