clock synchronization circuit

Abstract

Abstract PURPOSE:To quicken the reception leading time and to prevent deterioration of reception characteristics by changing the operating count number of an up-down counter of a digital PLL used for synchronous detection depending on the presence of establishment of clock synchronization. CONSTITUTION:A base band signal received from an input terminal 12 is inputted to a differentiation circuit 13 and a reception clock is reproduced from the extracted reception clock component by using a digital PLL comprising a phase comparator circuit 14, an up-down counter 16, a variable frequency division circuit 17, a frequency division circuit 18, an oscillation circuit 19 and a crystal oscillator 20.An up-down counter 23 outputs an establishment of clock synchronization to a count control circuit 15 and the operation count number of the up-down counter 16 is changed.

Inventors

• 👤 Tetsuaki Nakanishi
• 👤 徹明 中西

Bibliographic Details