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JPS6158317A Expired / Lapsed JP ⏱️ 0.0 years remaining

Internal bus circuit

Assignee: NEC Corp
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Filing: 1984-08-30
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Granted: —
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Expires: 2004-08-30
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Abstract

Abstract PURPOSE:To prevent influence of the change in bus signal to other circuits, suh as register cell, etc., when the operating speed is increased, by providing a means which receives bus signals, detects and amplifies the change in bus signal, and feeds back the amplified change to an internal bus. CONSTITUTION:An internal bus 21 is precharged when a precharging transistor 27 is conducted by a precharge signal PR1. When a low level is transferred at the transferring cycle of data thereafter, discharging takes place by a discharging transistor in a register 22. When the level of the internal bus 21 becomes lower than the low-level discriminating level of a comparator 24, a pull-down transistor 26 is conducted through an NOR gate 25 and the discharging speed of the internal bus 21 is increased. Therefore, no influences are given to other circuits, such as register cell, etc., even when the operating speed is increased.

Inventors

  • 👤 Toshiyoshi Iwata
  • 👤 岩田 利喜

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 20:37
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096

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Total Claims: 0
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