Clock phase fine adjusting circuit

Abstract

Abstract PURPOSE:To enable fine adjustment of clock phases by providing an RC circuit and a comparator in a repeater of digital communication and using the junction capacity for the capacity of the RC circuit. CONSTITUTION:When a clock signal of waveform (1) is inputted, rise and fall parts are made dull as shown by a waveform (2). This is compared with reference voltage Vref by a comparator COMP and a signal of a waveform (3) is outputted. Here the time constant due to internal resistance Re of a transistor Q and the junction capacity C can be changed by changing the terminal voltage of junction capacity of an integrated circuit, and accordingly, its phase difference can be ajusted. Thus, as clock phases can be adjusted finely, the clock signal can be adjusted most suitably in a superhigh-speed repeating circuit.

Inventors

• 👤 Izumi Uchiyama
• 👤 内山　泉美
• 👤 Hiroo Kitasagami
• 👤 北相模　博夫
• 👤 Kazuo Yamaguchi
• 👤 一雄 山口
• 👤 Hiroshi Hamano
• 👤 宏 濱野

Bibliographic Details