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JPS6139635A Expired / Lapsed JP ⏱️ 0.0 years remaining

Higher harmonic noise eliminating method

Assignee: OSAKI DENKI KOGYO KK
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Filing: 1984-07-31
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Granted: —
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Expires: 2004-07-31
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Abstract

Abstract PURPOSE:To enable high-speed data transmission in a system that uses a power line as a signal transmission line, by storing higher harmonic noise of AC wave over one period of the AC wave, and subtracting stored noises from received signals. CONSTITUTION:In a stage where no signal is transmitted, AC wave and higher harmonic noise are sampled in a sampling circuit 3, and the result is converted to digital values and sotred in a storing circuit 6. When a signal is transmitted, renewal of memory is not made from that point of time, and a final stored value is inputted from the storing circuit 6 to an arithmetic discriminating circuit 7. On the other hand, a sampling value obtained by digital conversion of received signal is inputted to the arithmetic discriminating circuit 7 from an input terminal 1 through a filter 2 and the sampling circuit 3. The arithmetic discriminating circuit 7 makes subtraction of these two kinds of input signals, and outputs only signal component eliminating higher harmonic noise component.

Inventors

  • 👤 Mitsuaki Fukushima
  • 👤 福島 光明
  • 👤 Satoshi Komazawa
  • 👤 駒沢 聰
  • 👤 Etsuro Nakayama
  • 👤 悦郎 中山

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 16:56
CPC Classifications
H; H04; H04B; H04B3/00; H04B3/54; H04B2203/00; H04B2203/54; H04B2203/5404; H04B2203/5425; H04B2203/5462; H04B2203/5491

Claims Analysis

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References Cited (Backward Citations)

JPS60229549A Cited

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