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JPS6139619A Expired / Lapsed JP ⏱️ 0.0 years remaining

Clock pulse distributing circuit

Assignee: NEC Corp
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Filing: 1984-07-30
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Granted: —
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Expires: 2004-07-30
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Abstract

Abstract PURPOSE:To make adjustment of clock skew accurately in short time by connecting output and input of clock distributing circuits and measuring osicllation frequency of the loop. CONSTITUTION:A loop is formed by connecting one of output terminals 15 to an input terminal 10, and making the loop generate oscillation based on delay of each circuit by inputting starting pulse to a oscillation starting terminal 11. Difference of timing between output terminals 15 is found by measuring the frequency, and timing between output terminals 15 is adjusted at high accuracy by fine adjusting units 14. Accordingly, pulse inputted to the input terminals 10 can be distributed to output terminals 15 at high accuracy. Further, timing adjustment with other distributing system and adjustment of output pulse width of output terminals 15 can be made by adjustment in a coarse adjusting circuit 12 and a pulse width adjusting circuit 13.

Inventors

  • 👤 Takashi Nakahara
  • 👤 中原 俊

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-26 05:40
CPC Classifications
—

Claims Analysis

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References Cited (Backward Citations)

JPS5283041A Cited
JPS5814622A Cited

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