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JPS6132291A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory device

Assignee: Sony Corp
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Filing: 1984-07-24
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Granted: —
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Expires: 2004-07-24
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Abstract

Abstract PURPOSE:To simplify reading and writing by supplying a column address strobe signal at a reverse phase after row address strobe signals are supplied in a page mode to N-number of memory blocks divided into two parts each. CONSTITUTION:Digital color video signals of one frame written on memory blocks 1 and 2 are read out through an address control similar to the writing. At the time of reading, data as shown in the figure J is outputted from the memory block 1, while data as shown in the figure K is outputted from the memory block 2. Output data of the memory blocks 1 and 2 are alternately selected by a selector 6, and accordingly the digital color video signal can be read out as shown in the figure L. Thus a clock system can be simplified, and a substrate can be scaled down, thereby facilitating the layout of the substrate.

Inventors

  • 👤 Yoshimaru Maruno
  • 👤 芳丸 丸野
  • 👤 Katsutoshi Doi
  • 👤 土居 勝利

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 00:50
CPC Classifications
—

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