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JPS6130818A Expired / Lapsed JP ⏱️ 0.0 years remaining

Digital modulation method

Assignee: Panasonic Holdings Corp
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Filing: 1984-07-23
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Granted: —
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Expires: 2004-07-23
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Abstract

Abstract PURPOSE:To eliminate a DC component by limiting the number of bits 0s between bits 1s in a modulation code string to 1-8 and providing two modulation code groups in response to the C.D.S value of each modulation code. CONSTITUTION:An 8-bit data is inputted to a coder 3 together with an output of exclusive OR between outputs of a D.S.V calculation section 1 and of a polarity discriminating section 2, when a modulation code of a group A is selected when the exclusive OR is zero and a modulation code of a group B is selected when the OR is logical ''1'' and the result is outputted to a shift registe 4. The modulation code comprising 14-bit inputted to the shift register 4 is read by a clock and inputted to a synchronizing signal adding section 5 with serial output. The addition section 5 adds a synchronizing signal, and after NRZI modulation is applied at an NRZI modulation section, a recording section 7 applies recording onto a magnetic tape.

Inventors

  • 👤 Hiroaki Takeuchi
  • 👤 武内 宏壮

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 21:09
CPC Classifications
—

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