← Back to Patent Explorer
JPS61242018A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Toshiba Corp
•
Filing: 1985-04-19
•
Granted: —
•
Expires: 2005-04-19
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To secure the excellent electric contact which is highly reliable in a microscopic contact hole by a method wherein a low resistance layer, which comes in contact with the conductive layer located in a semiconductor substrate, is formed dividing into two layers through the intermediary of the contact hole. CONSTITUTION:An N<+> diffusion layer is formed on an Si semiconductor substrate 1 as a conductive layer 2. An insulating layer 3 is formed on said N<+> diffusion layer, and a microscopic contact hole 4 is perforated on the conductive layer 2. Subsequently, the first low resistance layer 6 is formed thereon. A film layer 7 is formed thereon. Then, said film layer 7 is etched back, and a film part 7' is left only on the part located on the contact hole formed region. Subsequently, the first low resistance layer 6 is removed by performing an etching, and the remaining part 6' only is left. Moreover, the film part 7' is removed by performing a plasma ashing. Then, the second low resistance layer 8 is formed thereon. Subsequently, a patterning is performed on said low resistance layer 8 and it is used as a wiring pattern.

Inventors

  • 👤 Yoshihide Nagakubo
  • 👤 長久保 吉秀

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 00:33
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag