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JPS6124094A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory device for semiconductor

Assignee: Hitachi Microcomputer System Ltd
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Filing: 1984-07-11
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Granted: —
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Expires: 2004-07-11
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Abstract

Abstract PURPOSE:To shorten a rewriting time of data in total by withdrawing a charge inputted by write-in voltage by higher voltage, and by making the length of an erasing time the same degree as that of a write-in time. CONSTITUTION:A boosting circuit 8 consists of switches MOSFETs Q1, Q2 connected in series with clamp diodes D1, D2 to form a fixed write-in voltage Vpp1 and an erasing voltage Vpp2 controlling the voltage generated by charge pump 10 generating far higher voltage than electric source voltage Vcc, pushing up the level gradually receiving supply of charge from electric source voltage Vcc supplied from the outside. The voltage boosted by a charge pump 10 is clamped by break down voltage of clamp diode to generate the stabilized write-in voltage Vpp1 and erasing voltage Vpp2. Thus, the time for rewriting all the data of EEPROM device will be largely shortened.

Inventors

  • 👤 Kazuaki Ujiie
  • 👤 氏家 和聡
  • 👤 Nobuyuki Sato
  • 👤 信之 佐藤
  • 👤 Masaaki Terasawa
  • 👤 寺沢 正明
  • 👤 Shinji Nabeya
  • 👤 鍋谷 慎二

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 17:51
CPC Classifications
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