Test pattern generation control method and device

Abstract

Abstract PURPOSE:To generates test patterns for devices to be tested at a high speed with small memory capacity by classifying the test patterns by kinds and accessing them independently. CONSTITUTION:The test patterns are classified by the kinds into scan patterns and primary patterns and stored previously in a pattern memory 17 by the kinds in the order of use during storage. Then, instructions are read out of addresses of a test sequence memory 11 under the control of a control part 13 and outputted to an address arithmetic part 12. The arithmetic part 12 generates information for specifying readout addresses of the pattern memory 17 by said instructions and accesses the pattern memory 17 independently by the kinds of the test patterns according to the generation order of the test patterns. Consequently, the test patterns generated by combining the scan patterns and primary patterns successively are obtained.

Inventors

• 👤 Kazuo Yamaguchi
• 👤 和夫 山口

Bibliographic Details