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JPS6116641A Expired / Lapsed JP ⏱️ 0.0 years remaining

Automatic multiplex delay system

Assignee: NEC Corp
•
Filing: 1984-07-03
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Granted: —
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Expires: 2004-07-03
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Abstract

Abstract PURPOSE:To set automatically the delay of a transmission line by correcting the delay time of the transmission line of multiple constitution through firmware during initialization, and holding data on it. CONSTITUTION:A delay correcting circuit 103 receives input signals from highways 105a-108a and judges how long the highway input signals need to be delayed on the basis of memory data, thereby outputting highway output signals to highways 105b-108b. When initializing operation (POW ON RESET) is performed, a pilot pattern signal outputted from the delay correcting circuit 103 is monitored by a microprocessor 102 and memory contents are updated until a pilot pattern is outputted to the highways 105b-108b at the same time. The delay correcting circuit 103 varies the delay time successively when the memory contents are altered.

Inventors

  • 👤 Shohei Sato
  • 👤 昌平 佐藤
  • 👤 Hiroshi Inomata
  • 👤 浩 猪股

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 16:43
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04J3/0629

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