← Back to Patent Explorer
JPS6097665A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory

Assignee: Fujitsu Ltd
•
Filing: 1983-11-01
•
Granted: —
•
Expires: 2003-11-01
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To bypass a word line by a single layer wiring with low resistance value while forming a low resistance wiring perpendicular to the word line by a method wherein a wiring formed of the second wiring layer with relatively low resistance value traversing a cut off point of a bypass wiring is provided. CONSTITUTION:A word line 6 and a transfer gate 7 commonly used for another transfer gate to be the second layer polycrystalline layer are formed. Then an interlayer insulating film made of SiO2 is formed and after forming an electrode hole on the interlayer insulating film, a bit line 8 made of molybdenum silicide is formed. Next the interlayer insulating film is formed again and after forming an electrode contact hole on the interlayer insulating film, a bypass wirings 9, 10 made of Al are formed. When low resistance value is required for any line other than the word line, the bypass wirings 9 or 10 of the word line 6 may be cut off halfway leaving e.g. the word line 6 of molybdenum silicide only in the cut off section wherein a wiring perpendicular to the word line 6 such as cell plate power supply line etc. is formed.

Inventors

  • 👤 Masao Taguchi
  • 👤 眞男 田口

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 19:34
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

JPS5835968A Cited
JPS5854654A Cited
JPS58148939U Cited

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag