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JPS6095973A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1983-10-31
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Granted: —
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Expires: 2003-10-31
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Abstract

Abstract PURPOSE:To obtain a semiconductor device which not only operates at high speed with low power consumption but also has a high integration degree and which is desirable for electronic computers or the like, by providing on a semiconductor substrate a transistor element as a driver and an inverter circuit having an N-shaped negative resistance element as a load. CONSTITUTION:A drain of enhancement-mode FET element 11 to serve as a driver and an N-shaped negative resistance element 12 are connected in series between a supply voltage VDD and a ground voltage to provide a semiconductor device. More particularly, AlxGa1-xAs layers 22-28 each of which has a specified thickness, a donor concentration and an (x) value are layered on a semiinsulating GaAs substrate 21 and caused to grow by molecular beam epitaxy. The region as shown by A of the structure thus obtained is used for a heterojunction- type FET element of enhancement mode, while the region as shown by B is used for an N-shaped negative resistance element. Thus, the layered structure is divided into the regions by a predetermined depth, and the region A is provided with a gate electrode 30 and with source and drain electrode 31 and 32 on both sides of the electrode 30, while a supply line 33 is connected to the region B.

Inventors

  • 👤 Takashi Mimura
  • 👤 高志 三村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 23:01
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80

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