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JPS609241A Expired / Lapsed JP ⏱️ 0.0 years remaining

Synchronizing protection system

Assignee: NEC Home Electronics Ltd
•
Filing: 1983-06-28
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Granted: —
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Expires: 2003-06-28
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Abstract

Abstract PURPOSE:To realize the optimum forward protection capacity for a PCM communication device by changing the set value of a discordance number counter in accordance with the reception signal level. CONSTITUTION:The signal transmitted from a transmission line is applied to a synchronism detection circuit 3 via a demodulating circuit 2 in the form of the data signal and bit clock. The synchronizing signal is extracted out of each frame. The signal level value obtained from a detecting circuit 13 is turned into the n-bit numerical value after sampling/holding and A/D conversion, and an ROM16 is addressed. The optimum value N2 to the code error factor corresponding to the reception signal level is written to the ROM16. As a result, the set count value N2 of a discordance number counter 7 varies automatically in response to the change of the output signal level value of the circuit 13. Thus the forward protection is always secured in an optimum state even though the reception signal level varies in terms of time.

Inventors

  • 👤 Yukihiro Okada
  • 👤 行弘 岡田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 00:31
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/042

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