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JPS609154A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory and its manufacturing method

Assignee: Hitachi Ltd
•
Filing: 1983-06-29
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Granted: —
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Expires: 2003-06-29
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Abstract

Abstract PURPOSE:To obtain large electrostatic capacity with a small substrate area by forming a memory capacitor for a dRAM in multilayer structure as being used in a variable capacitor. CONSTITUTION:When manufacturing a capacitor having multilayer structure of two layers or more consisting of a semiconductor and an insulating film, impurity ions 6 are implanted selectively to the N type semiconductor 7 by using a mask 5 through ion implantation technique, and P<+> layers 8 are formed in the semiconductor. When the ions are implanted several times while changing the energy of the implantation, a plural layer of the P<+> layers are introduced into Si. Only the P<+> layers are removed through selective etching. The surface of the semiconductor is coated with an oxide film 3 by using a thermal oxidation method, etc. When the oxide film is coated with a high conductivity polycrystalline Sig through CVD, a desired capacitor is completed. Accordingly, an area and depth occupying in the surface of a semiconductor layer of the capacitor can be manufactured in small values, and sufficient electrostatic capacity can be provided to the capacitor.

Inventors

  • 👤 Masahiro Shigeniwa
  • 👤 昌弘 茂庭
  • 👤 Masanobu Miyao
  • 👤 正信 宮尾
  • 👤 Osamu Okura
  • 👤 理 大倉
  • 👤 Kikuo Kusukawa
  • 👤 喜久雄 楠川
  • 👤 Yoshio Sakai
  • 👤 芳男 酒井
  • 👤 Hideo Sunami
  • 👤 英夫 角南

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 14:21
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/01; H10B12/02; H10B12/03

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