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JPS6090408A Expired / Lapsed JP ⏱️ 0.0 years remaining

Automatic level control circuit

Assignee: Toshiba Corp
•
Filing: 1983-10-24
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Granted: —
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Expires: 2003-10-24
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Abstract

Abstract PURPOSE:To reduce signal distortion and perform high-precision control by varying the gain of a variable gain amplifier stepwise at specific intervals, and controlling this gain linearly according to the value of a counter which counts a clock according to an output level. CONSTITUTION:An output voltage e0 is detected by a level detector 20 and the counting-up or -down operation of the 1st counter 42 is specified according to whether the output E0 is larger than a reference voltage Er, thereby counting the clock CP. A shift-up output KD or shift-down output KU is sent to the 2nd counter 43 with the carry C or borrow B of the counter 42 to turn on one of FETs 161-169 according to the counted value of the 2nd counter 43. Resistances 151-159 are so set as to vary the gain of the amplifier 10 linearly, so the gain is controlled linearly according to the output voltage and signal distortion is reduced to perform high-precision level control.

Inventors

  • 👤 Toshitaka Fujii
  • 👤 敏孝 藤井
  • 👤 Akio Goto
  • 👤 後藤 昭夫

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 22:10
CPC Classifications
H; H03; H03G; H03G1/00; H03G1/0005; H03G1/0088; H03G3/00; H03G3/20; H03G3/30

Claims Analysis

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References Cited (Backward Citations)

JPS55157113A Cited

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