Processor for multiple virtual storage data

Abstract

Abstract PURPOSE:To access a cache memory with logical addresses and reduce an overhead in task switching by providing a recognizer for recognizing which task data in the cache memory belongs to. CONSTITUTION:The cache memory 3A consists of a data memory part 3A3 for holding a copy of part of data in a main memory, a directory part 3A3 for checking whether data in an address requested from a basic processing part 3B is present in the data memory part 3A3 or not, and a control part 3A1 for controlling the operation of the cache memory 3A. When the data is present in the data memory part 3A3 in read operation, the cache memory 3A transfers it to the basic processing part 3B through a signal line 3C6. Write data is received from the basic processing part 3B in write operation and when there is a write address present in the data memory part 3A3, the received data is written there.

Inventors

• 👤 Hidekazu Matsumoto
• 👤 松本　秀和
• 👤 Tadaaki Bando
• 👤 忠秋 坂東
• 👤 Shinichiro Yamaguchi
• 👤 伸一朗 山口
• 👤 Takeshi Kato
• 👤 猛 加藤
• 👤 Kenji Hirose
• 👤 健二 廣瀬

Bibliographic Details