Complementary semiconductor integrated circuit

Abstract

Abstract PURPOSE:To simplify a clock input signal by connecting N channel FETs and P channel FETs alternately between resistors as a transmission gate. CONSTITUTION:The N channel FETs 10, 12 and the P channel FETs 11 are alternately connected between register circuits 31-3n as transmission gates respectively. The register circuits 31-3n are coupled by passage control transistors (TRs) such as the N channel FET10, P channel FET11 and N channel FET12 in series. The gates of the passage control type TRs are connected to clock input terminals 7 and the odd number-th passage control type TR is formed by an N channel FET and the even number-th passage control type TR is formed by a P channel FET respectively. Since the C-MOS shift register is formed as shown above, a clock input signal can be simplified.

Inventors

• 👤 Yuichi Saito
• 👤 斎藤　祐一

Bibliographic Details