Semiconductor integraged circuit device

Abstract

Abstract PURPOSE:To increase the speed of an LSI by isolating only a transistor, parasitic capacitance between a collector and a substrate therein is regarded as substantial, through a U groove isolation method and isolatng another transistor through an oxide-film isolation method. CONSTITUTION:N<+> buried layers 2, an N<-> type epitaxial layer 3, an oxide film 4 and a nitride film 5 are formed on a semiconductor substrate 1 consisting of P type silicon in succession, oxide films 7 for isolation are shaped where an element is isolated by the oxide films, and U grooves 9a, 9b are formed where the element is isolated by the U grooves. Oxide films 10 are formed in the U grooves 9a, 9b, the insides of the U grooves are filled with polysilicon 11, and oxide films 12 are shaped to the surface of the polysilicon, thus constituting U- groove isolation regions 13. The ions of an impurity are implanted, the impurity is thermally diffused, and P<+> type diffusion layers 14 for bases, N<+> type diffusion layers 15 for emitters and N<+> type diffusion layers 16 as collector leading- out ports are formed simultaneously to both sections on the oxide-film isolation side and the U-groove isolation side.

Inventors

• 👤 Toru Kobayashi
• 👤 徹 小林
• 👤 Hiroshi Hososaka
• 👤 細坂　啓
• 👤 Mitsuo Usami
• 👤 光雄 宇佐美
• 👤 Akihisa Uchida
• 👤 明久 内田
• 👤 Motonori Kawaji
• 👤 河路　幹規

Bibliographic Details