Clock signal generator

Abstract

Abstract PURPOSE:To prevent occurrence of out of phase and unnecessary pulse by providing a register that can hold the value of clock output and an ordinary register and synchronizing the hold control timing by a wave front differentiation circuit. CONSTITUTION:An oscillator 1 generates reference clock in a clock signal generating device. A frequency divider 2 divides output of the oscillator to 1/integer. A wave front differentiation circuit 5 wave front differentiates the output of the frequency divider 2. An AND circuit 7a outputs logical product of output of an FF6a that stores start command and output of the circuit 5. Thus, as a controlling signal to a selector circuit 4 is outputted when output of the divider 2 is ''H'', the phases of clocks of registers 3b, 3a become equal. An AND circuit 7b outputs logical product of output of an FF6b that stores hold command and output of the circuit 5. Thus, as controlling signal to the selector 4 is outputted when output of the divider 2 is ''H'', output of the register 3b and output of the register 3a become the same phase.

Inventors

• 👤 Noriaki Sakuma
• 👤 佐久間　則明

Bibliographic Details