JPS6049415A
Expired / Lapsed
JP
⏱️ 0.0 years remaining
Power supply circuit
Assignee: Toshiba Corp
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Filing: 1983-08-29
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Granted: —
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Expires: 2003-08-29
Abstract
Abstract PURPOSE:To reduce greatly the chip area for integration by using an npn transistor to form a feeding transistor of a feed circuit. CONSTITUTION:A feed circuit 10 is provided between a power supply voltage generating circuit 2 and a feeder 1a. The circuit 10 consists of a resistance 11 and a feeding npn transistor TR12. A protecting circuit 20 is provided with a voltage drop detecting circuit 22 and a protecting npnTR21. A feedback circuit 30 actuates the TR12 and TR21 with a constant current respectively. In such a constitution of the circuit 10, the chip area can be greatly reduced for integration.
Inventors
- 👤 Tatsuhiro Osanawa
- 👤 長縄 達博
- 👤 Yutaka Nishino
- 👤 豊 西野
- 👤 Takashi Saeki
- 👤 隆 佐伯
- 👤 Hisashi Yamada
- 👤 尚志 山田
Bibliographic Details
Application Number
—
Jurisdiction
JP
Data Source
google_patents
Last Synchronized
2026-11-01 23:36
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/56
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