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JPS6047418A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor exposing device

Assignee: Hitachi Ltd
•
Filing: 1983-08-25
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Granted: —
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Expires: 2003-08-25
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Abstract

Abstract PURPOSE:To achieve the high accuracy in overlapping when exposure is performed for each chip or each field by the step- and repeat-method by measuring the error of arrangement among the chips or the field already formed to correct the quantity of movement of a wafer stage based on that memorized error. CONSTITUTION:The wafer transported from a supply track 52 is roughly orientated on a pre-alignment stage 53 at first and then it is set on a stage for measuring arrangement error 50 by a handling mechanism. Next, the wafer 55 placed on this stage is corrected in its theta quantity of rotation by the alignment scopes for theta correction 57 and 58 the relative positional relation of which is already known. Then, while the wafer is moved by the step- and repeat-method, an arrangement error is measured by the scope for measuring arrangement error 56 and is stored in a memory. After that, the wafer is transferred to an exposure stage 51 by an arm 59 and this wafer 60 is further corrected in its theta quantity of rotation by the alignment scopes for theta correction 61 and 62. Subsequently, the wafer is positioned under a reduction lens of the exposing device.

Inventors

  • 👤 Masataka Shiba
  • 👤 正孝 芝
  • 👤 Yasuo Nakagawa
  • 👤 中川 泰夫
  • 👤 Yoshisada Oshida
  • 👤 良忠 押田
  • 👤 Mitsuyoshi Koizumi
  • 👤 小泉 光義
  • 👤 Toshihiko Nakada
  • 👤 俊彦 中田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 13:50
CPC Classifications
G; G03; G03F; G03F9/00; G03F9/70; G03F9/7003; G03F9/7046; G03F7/00; G03F7/70; G03F7/70691; G03F7/70716; G03F7/70725

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