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JPS6042828A Expired / Lapsed JP ⏱️ 0.0 years remaining

Method for aligning mask

Assignee: NEC Corp
•
Filing: 1983-08-18
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Granted: —
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Expires: 2003-08-18
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Abstract

Abstract PURPOSE:To reduce the occupation area in a chip by reducing the number of blocks by using diagonal patterns as the basic compositions of shapes of the aligning patterns used for the manufacture of ICs. CONSTITUTION:In the 1st process, positioning for alignment is performed as shown in FIG. (a). In the 2nd process, alignment is performed with using a diagonal pattern as shown in FIG. (b) followed by exposure. In the 3rd process, the pattern divided into four pieces is used as shown in FIG. (c) and in the subsequent 4th process, the pattern as shown in FIG. (d) is used. After that, in the 5th process, the rhombic pattern as shown in FIG. (e) is used for exposure. In the 6th process, the diagonal pattern similar to those of FIGs. (b) and (d) is used as shown in FIG. (f) for exposure. Thus, the six aligning patterns shown in FIGs. (a)-(f) are arranged in a large rectangular block so as to reduce the number of blocks.

Inventors

  • 👤 Masayuki Sugiyama
  • 👤 正幸 杉山

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 13:12
CPC Classifications
G; G03; G03F; G03F9/00; G03F9/70; G03F9/7073; G03F9/7076

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