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JPS604253A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit memory

Assignee: NEC Corp
•
Filing: 1983-06-23
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Granted: —
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Expires: 2003-06-23
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Abstract

Abstract PURPOSE:To improve the integration density by reforming the wiring structure, in the title device having a static type memory cell using a double-layer metallic wiring. CONSTITUTION:A field insulation film 12, a gate insulation film 13, and diffused layers 14, 15, and 16 are formed on a semiconductor substrate 11 by a normal method. A word line 6 connected to an MOSFET is formed by the formation of the first polycrystalline Si layer 17, which line is then insulated with an interlayer insulation film 18, and a power source line 5 and a resistor R connected thereto are formed by means of the second polycrystalline layer. A ground line 1 made of the first Al layer is formed by insulation with an interlayer insulation film 19, which line is then insulated by being covered with an interlayer insulation film 20, and data lines 3 and 4 are formed thereon in the direction rectangular to the ground line by means of the second Al layer. Since the area required for wiring can be thus reduced, the integration density can be improved by said reduction amount.

Inventors

  • 👤 Masahiko Honda
  • 👤 本田 政彦

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 20:11
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10B; H10B10/00; H10B10/15; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS56161668A Cited
JPS5773968A Cited
JPS5843568A Cited

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