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JPS6041264A Expired / Lapsed JP ⏱️ 0.0 years remaining

Transistor

Assignee: Hitachi Ltd
•
Filing: 1984-07-20
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Granted: —
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Expires: 2004-07-20
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Abstract

Abstract PURPOSE:To facilitate the integration by providing a semiconductor layer having a metal lattice on a semi-insulating substrate, and providing the first electrode on the upper surface of a semiconductor layer and an impurity region connected to the second electrode on the upper surface of the semiconductor layer on the lower surface. CONSTITUTION:A semiconductor layer 3 for forming a current path is provided on a GaAs semi-insulating substrate 1. A metal lattice made of tungsten film 4 is arranged in the layer 3 to form a base. S ions are implanted to the lower surface of the layer 3 to form an N<+> type layer 2, connected to a contacting electrode 8 on the upper surface of the layer 3 through an N<+> type layer 5, and an emitter electrode 7 is provided on the upper surface of the layer 3. Since the electrode 7 and a collector electrode 8 are led to the upper surface of the substrate, the integration can be facilitated, and since the semi-insulating substrate is used, the floating capacity can be reduced.

Inventors

  • 👤 Hisao Nakajima
  • 👤 尚男 中島
  • 👤 Susumu Takahashi
  • 👤 進 高橋
  • 👤 Tadashi Fukuzawa
  • 👤 董 福沢
  • 👤 Hironori Tanaka
  • 👤 田中 広紀

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 07:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80

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