Vertical type mosfet

Abstract

Abstract PURPOSE:To reduce both ON-resistance and threshold voltage of the titled MOSFET by a method wherein the surface of a P-well, to be positioned between the N type Si substrate to be turned to the main electrode of one side and the N-well to be turned to the main electrode on the other side, is inclined against the surface of a substrate and a gate electrode is arranged through the intermediary of an insulating film. CONSTITUTION:An etching is performed on the main surface of a substrate 3 having an N-epitaxial layer 2 and a slunting face is formed on an N<+> type Si substrate, a gate oxide film 5 and a poly Si electrode 6 are selectively arranged, and a P-well 8 is formed. Then, a P-well 11 to be used to lead-out electrode is formed in the center of the well 8, and an N<+> source 9 is formed by performing a double diffusion using an electrode 6 as a mask. The above is covered by a PSG12, an aperture 13 is provided, and an Al electrode 14 is attached. According to this constitution, a channel part CH is formed on the slunting face 10, channel effect can be blocked without changing the threshold voltage of the vertical type FET, which will be determined by the impurity density on the junction face of the well 8 and the N-source 9, for the N type drain layer of high impurity density due to the lowering of ON-resistance, thereby enabling to obtain the device having low ON-resistance and threshold voltage.

Inventors

• 👤 Tamotsu Tominaga
• 👤 富永　保

Bibliographic Details