Switching system of packet switchboard

Abstract

Abstract PURPOSE:To prevent stored contents in memories of both systems from disaccord with each other after transfer by indicating the write inhibition, which is accompanied with reception of a new packet in the second memory of the current system, in a communication control part of the current system from a processing part of the current system. CONSTITUTION:When a packet is received by line corresponding parts 61-6n, the packet reaches a communication control part 21 of the current system. The received packet is divided to a fixed-length part including a header part and the remainder part, and data is stored in the second memory 31 of the current system, and the header part is transmitted to a central processing part 11 of the current system. In case of switching from the current system to the stand-by system, the central processing part 11 of the current system outputs commands for the write inhibition, which is accompanied with reception of a new packet in the second memory 31 of the current system 31, and for confirmation of the write end to the communication control part 21 of the current system. Thereafter, the central processing part 11 instructs the communication control part 21 to transfer data to a memory 32 of the stand-by system by DMA.

Inventors

• 👤 Ryuichi Toki
• 👤 土岐　隆一
• 👤 Mineo Nishiwaki
• 👤 西脇　峰雄

Bibliographic Details