Semiconductor integrated circuit

Abstract

Abstract PURPOSE:To improve the integrity without increasing an area of a wiring zone by a method wherein the 1st layer and the 3rd layer wirings are provided to the wiring zone between basic cell-rows of a master slice integrated circuit along the direction of the cell-rows and connected to terminals lead-out by the 2nd layer wiring. CONSTITUTION:A wiring zone 22 is provided between basic cell-rows 211 and 222 and the 1st layer wiring 23, the 2nd layer wiring 24 and the 3rd layer wiring 25 are provided to the wiring zone 22. The 1st layer wiring 23 and the 3rd layer wiring 25 have channels A1-A3 and B1-B3 which are parallel to the basic cell-rows 211, 212. A discrepancy of a half pitch is provided between the channels A1-A3 and the channels B1-B2. Terminals of the basic cells are led-out by the 2nd layer wiring 24. Wirings between the basic cells are achieved by connecting these terminals and the channels A1-A3, B1-B3 with through- holes.

Inventors

• 👤 Masazumi Shioji
• 👤 正純 塩地

Bibliographic Details