Dividing device

Abstract

Abstract PURPOSE:To curtail the quantity of hardware for retrieving forecasting partial quotient from a table by constituting hierarchically a table for retrieving the forecasting partial quotient from a divisor register, as a result of addtion and subtraction. CONSTITUTION:A divisor is stored in a divisor register 1, inputted to a multiple generating circuit 2, and the multiple generating circuit 2 receives a partial quotient forecasting signal (m) from a partial quotient forecasting circuit 3, and generates divisors of -15, -14,...0, +1, +2,...+15 times, in case when a radix is 16. The partial quotient forecasting circuit 3 calculates a value of (m) of (m)X DSR to be added and subtracted in the next time, from an output of a carry propagation adder (CPA)5 and an output of the divisor register (DSR)1. In a non- recovery type division when the radix is 16, when determining high-order 4 bits, in (m) of 5 bits containing an essential code, it is sufficient by high-order 5 bits of the CPA and high-order 6 bits (essential 9 bits) of the DSR. The CPA and (m) prepare a table of 5 bits and 4 bits, respectively, as a rough forecasting, (m) is derived from the CPA (5 bits) and the DSR (6 bits), and in case of a precise forecasting for correcting (m), a correcting table of the CPA 6 bits and (m) is prepared, and the least significant bit of (m) is derived.

Inventors

• 👤 Masayuki Ikeda
• 👤 正幸 池田

Bibliographic Details