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JPS60201415A Expired / Lapsed JP ⏱️ 0.0 years remaining

Power source circuit

Assignee: NEC Corp
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Filing: 1984-03-26
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Granted: —
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Expires: 2004-03-26
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Abstract

Abstract PURPOSE:To obtain an integrated circuit which can realize a low power consumption irrespective of whether a consumed current is large or small, by combining an n channel type depression FET and an npn type bipolar transistor. CONSTITUTION:The collector, the base and the emitter of an npn type TRQ2 are connected to a power supply voltage VDD, the source of an FETQ1, and a power supply voltage VLOG of an integrated circuit, respectively. As a result, a current which can be made to flow to an integrated circuit L can be set to a current gain multiple of the TRQ2, and also a temperature coefficient can be set to zero.

Inventors

  • 👤 Akira Yazawa
  • 👤 矢沢 晃

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 10:51
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20

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