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JPS60200773A Expired / Lapsed JP ⏱️ 0.0 years remaining

Controller for inverter

Assignee: Tokyo Sanyo Electric Co Ltd
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Filing: 1984-03-26
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Granted: —
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Expires: 2004-03-26
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Abstract

Abstract PURPOSE:To obtain a controlled suppressed in the capacity of a memory cell to the minimum limit by separately storing the combination state of ON and OFF of switching elements and the maintaining time of the combination state, and obtaining a PWM output in combination with both. CONSTITUTION:The first memory 10 in which the combination states of the ON and OFF of switching elements are stored and the second memory 11 in which the maintaining time of the combination states is stored are provided in a controller of a 3-phase bridge circuit using a plurality of swtiching elements. The sequence of the combination obtained continuously for a sinusoidal wave and the maintaining time are read out from the both memories 10, 11 in response to the frequency set by a frequency setter 8, and continued PWM outputs X, Y,... are output to the swtiching elements by a timer 13 and a controller 14.

Inventors

  • 👤 Kiyoshi Itani
  • 👤 猪谷 潔
  • 👤 Hisashi Tokisaki
  • 👤 久 時崎
  • 👤 Tomohide Funakoshi
  • 👤 智英 船越
  • 👤 Nobuo Otsuka
  • 👤 信男 大塚
  • 👤 Katsuhiro Okubo
  • 👤 大久保 勝寛
  • 👤 Hikari Katsuki
  • 👤 香月 光

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 23:23
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/042; G05B19/0423

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