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JPS60193333A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Panasonic Holdings Corp
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Filing: 1984-03-15
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Granted: —
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Expires: 2004-03-15
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Abstract

Abstract PURPOSE:To easily obtain an electrode having a small thickness when forming a two-layer wiring electrode on the surface of an Si substrate, by providing, in a layered manner, a polycrystalline Si film having a predetermined shape and containing a low-density impurity and a metallic film having a high melting point and containing an impurity, and heat treating them to cause uniform planer reaction on the interface thereof. CONSTITUTION:An extremely thin gate oxide film 2 is produced on the surface of an Si substrate 1 by heat treatment. A polycrystalline Si film 3 containing little impurity and a W silicide film 4 containing a high-density impurity are layered and deposited on the film 2. Unrequired portions of the films 4 and 3 are removed by gas plasma with the use of CCl4 or the like, so that a gate electrode having a desired shape and consisting of the films 3 and 4 is left. The structure is then subjected to heat treatment in N2 gas to reduce the resistance of the film 4 and to diffuse the impurity in the film 4 into the film 3 to reduce the electrode resistance. The whole surface is then covered with an SiO2 film 5 and an aperture is provided. An Al electrode 6 is fixed on the film 4 exposed by providing the aperture. In such a manner, a thin electrode is obtained without decreasing the dielectric strength.

Inventors

  • 👤 Masanori Fukumoto
  • 👤 正紀 福本
  • 👤 Shohei Shinohara
  • 👤 篠原 昭平
  • 👤 Shozo Okada
  • 👤 岡田 昌三
  • 👤 Juro Yasui
  • 👤 安井 十郎
  • 👤 Koichi Kugimiya
  • 👤 公一 釘宮

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 08:24
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011

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