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JPS6016784A Expired / Lapsed JP ⏱️ 0.0 years remaining

Variable length coding circuit

Assignee: Hitachi Ltd
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Filing: 1984-06-27
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Granted: —
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Expires: 2004-06-27
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Abstract

Abstract PURPOSE:To reduce the picture transmission cost and picture recording cost by utilizing organically a sub-Nyquist sampling and variable length DPCM to code a picture signal very efficiently. CONSTITUTION:A DPCM code D0,0 inputted to a terminal 1 is delayed and a DPCM code D1,-1 of a picture element at the upper right of the code D0,0 is obtained as an output. This delayed output code D1-1 is converted into a representative, i.e., a gradient of luminance by a representative converting circuit 3, and from the result a signal delayed by one sampling period is obtained by a register 4. An average value of the signal before and after the delay is obtained from an adder circuit 5 and a coefficient circuit 6, and an imaginary DPCM code D'0,-1 corresponding to an imaginary picture element just above the code D0,0 is obtained by quantizing the average value by a DPCM quantizing circuit 7. The codes D'0,-1, D0,0 are inputted to a code converting circuit 8, the code D0,0 is converted into a code suitable for the variable length referencing the D'0,-1, and this is subject to variable length coding by a code converting circuit 9 and the result is outputted to a terminal 10.

Inventors

  • 👤 Masahiko Achiha
  • 👤 征彦 阿知葉

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 17:53
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/50

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