Digital type electronic tuning system

Abstract

Abstract PURPOSE:To attain the reception in the range of correct tuning even if there is a variation in a ceramic filter at the preset channel selection using a PLL loop by employing a voltage synthesizer system for the PLL synthesizer system. CONSTITUTION:When a PLL loop is locked by the PLL operation, an output signal is generated from a lock detecting circuit 23, and when a broadcast signal exists in this state, an SD signal is generated from an IF level detecting circuit 24. Then a signal throwing a switch 22 to the position S is outputted from a control circuit 21 and the operation is changed over from the PLL operation to the AFC operation. Thus, an S curve signal of a detecting circuit 6 is amplified by a DC amplifier 12 and applied to a charge pump 13. An output signal of the pump 13 is converted into a DC voltage by a low pass filter 11 and applied to a local oscillating circuit 10 and a varactor of a radio frequency amplifier circuit 3, then the receiver is brought into the correct tuning state.

Inventors

• 👤 Shigehiko Ikeguchi
• 👤 池口　滋彦
• 👤 Hiroshi Tanaka
• 👤 田中　紘資

Bibliographic Details