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JPS60154633A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Hitachi Microcomputer System Ltd
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Filing: 1984-01-25
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Granted: —
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Expires: 2004-01-25
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Abstract

Abstract PURPOSE:To reduce processes of forming conductive layers for bonding a wired substrate to a package substrate of a semiconductor device, by providing on the rear face of the wired substrate a conductive layer consisting of the same metallic material with a conductive layer for forming electrodes on the upper face of the wired substrate. CONSTITUTION:An LSI chip 1 is electrically and mechanically connected from its Si to a wired substrate 2 through pipe electrodes 3. On the Al wiring on the wired substrate 2, formed are conductive layers of Cr-Cu-Au, on which a Pb/Sn layer is formed to facilitate bonding. Conductive layers of Cr-Cu-Au are formed on the rear face of the wired substrate 2 and a Pb/Sn conductive layer 7 is vapor deposited on the Au layer and is bonded to a package substrate 4 consisting of electrically insulating SiC through Au paste 6. In such a manner, both of the conductive layers on the upper and lower faces of the wired substrate can be vapor deposited simultaneously and thus the number of the assembling processes can be reduced.

Inventors

  • 👤 Kazuyoshi Sato
  • 👤 和善 佐藤
  • 👤 Minoru Enomoto
  • 👤 榎本 実
  • 👤 Michio Yamashita
  • 👤 道男 山下
  • 👤 Toshihiko Sato
  • 👤 俊彦 佐藤
  • 👤 Yasuyuki Yamazaki
  • 👤 康行 山崎

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 22:53
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/07251; H10W72/20; H10W72/251; H10W72/252

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