Semiconductor ic device

Abstract

Abstract PURPOSE:To prevent the malfunction of an analog IC from a large load of inductance by a method wherein, using a substrate of the same conductivity type as that of a collector layer, a reverse conductivity type layer and the substrate are connected to a reference potential by interposing the reverse conductivity layer between the substrate and the collector layer. CONSTITUTION:N<+> layers 13 are buried in a P-epitaxial layer 12 on the N type Si substrate 11, and N-collector layers 14a and 14b are produced by isolating an N-epitaxial layer 14 with a P<+> layer 15. An N-substrate connection layer 16, N<+> collector connection layers 17, P-base layers 18, N<+> emitter layers 19, an N<++> collector lead-out layer 20 are provided, and an electrode is attached to each. When the collector layer 14a of an L-load driving element T1 is biased negatively to the grounded substrate 11 and P-layer 12 by application of a negative high-voltage generating by load-off on the layer 14a, a parasitic bi-polar transistor T3 whose emitter is the layer 14a generates under the element T1, and the transistor T1 becomes saturated by supply of current from the substrate 11. Thereby, a parasitic transistor is not formed between the adjacent element T2, and the collector potential of the element T2 does not decrease, resulting in normal actions of the element T2.

Inventors

• 👤 Chikara Tsuchiya
• 👤 主税 土屋

Bibliographic Details