Lead frame for semiconductor device
Abstract
Abstract PURPOSE:To provide a lead frame with excellent adhesion to a mold resin and with highly solderable outer lead sections by a method wherein regions to meet the mold resin and the outer lead sections on a substrate, with its entire surfaced plated with Cu, are provided with plated Sn or an Sn alloy layers and a wire bonding section and die bonding section are covered with an Ag or Au layer. CONSTITUTION:The entire surface of a substrate 10 composed of Fe or an Fe alloy is plated with Cu, and several sections in the Cu coating 8 including regions to meet a mold resin and the outer lead sections are plated with a layer 9 of Sn or Sn-Ni or the like. Further, a die bonding and wire bonding sections in the Cu coating 8 are provided with an Ag layer 6 by plating. Au may be used instead of Ag. When the product is to be used as a semiconductor device, a semiconductor element 5 is fixed to the die bonding section, connected by Au lines or the like to the wire bonding section, and is finally sealed off by a mold resin 7 for the constitution of a semiconductor device. The mold resin runs easily on the surface coated with Sn or an Sn alloy and the surface has an excellent affinity with the mold resin to be hardened later.
Inventors
- 👤 Yoshihiro Matsuyama
- 👤 松山 圭宏
- 👤 Masaru Watanabe
- 👤 勝 渡辺
- 👤 Mamoru Onda
- 👤 護 御田
- 👤 Ryozo Yamagishi
- 👤 山岸 良三
- 👤 Osamu Yoshioka
- 👤 修 吉岡
- 👤 Yoshiaki Wakashima
- 👤 若島 喜昭
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.