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JPS60147136A Expired / Lapsed JP ⏱️ 0.0 years remaining

Electrode and wiring for semiconductor device

Assignee: Hitachi Ltd
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Filing: 1984-01-11
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Granted: —
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Expires: 2004-01-11
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Abstract

Abstract PURPOSE:To prevent any implanted ion from hitting metal crystal grid causing channel phenomenon by a method wherein multiple crystal particles with different crystal arrangement are deposited in vertical direction to film surface. CONSTITUTION:A gate SiO2 film 2 and a specified step difference 3 are formed on an Si substrate 1 and then a W-film 4 is formed by sputtering process using normal Ar gas under heated status at the substrate temperature of e.g. 800 deg.C. Then after forming the W-film 4 into a specified gate electrode 4' and a wiring shape 4'' by reactive sputter etching process, As ion is implanted therein. Later the surface is heattreated and a junction layer 5 such as source, drain of an MOS transistor, an insulating film 6, Al electrodes 7, 7' for leading out are formed to make up an MOS type integrated circuit. Through these procedures, different from the case of forming at the substrate temperature not exceeding 300 deg.C, a film with three or four crystal particles deposited may be formed in the direction to the surface of the W-film without forming columnar crystalline structure.

Inventors

  • 👤 Naoki Yamamoto
  • 👤 直樹 山本
  • 👤 Seiichi Iwata
  • 👤 誠一 岩田
  • 👤 Nobuyoshi Kobayashi
  • 👤 伸好 小林
  • 👤 Masao Kawamura
  • 👤 川村 雅雄

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 02:12
CPC Classifications
—

Claims Analysis

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References Cited (Backward Citations)

JPS57159042A Cited
JPS58191470A Cited
JPS58191473A Cited

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