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JPS60145641A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Toshiba Corp
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Filing: 1984-01-10
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Granted: —
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Expires: 2004-01-10
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Abstract

Abstract PURPOSE:To improve the chip integrating density by forming the wirings of the peripheral circuit of memory with less wiring layer from the wiring layers of the memory cell, thereby reducing the wiring area. CONSTITUTION:A semiconductor integrated circuit device of master/slice type has, for example, a logic circuit 1, a memory cell 2, a wiring region 3 between the memory and the logic unit, an I/O unit 4, and a peripheral circuit (decoder) 5 of the memory. Then, they are connected with less wiring layers than the memory cells of the peripheral circuit of the memory. Thus, the wiring layer of the upper layer from the wiring layer for forming the peripheral circuit of the memory is formed of the memory peripheral circuit, between the logic circuits, and between the logic circuit sections. Accordingly, the wiring region between the memory section and the logic unit can be reduced, the area of the logic unit is increased, the integration of the chip is improved.

Inventors

  • 👤 Masazumi Shioji
  • 👤 正純 塩地

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 11:49
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90

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