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JPS60136992A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory

Assignee: Hitachi Ltd
•
Filing: 1984-01-06
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Granted: —
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Expires: 2004-01-06
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Abstract

Abstract PURPOSE:To attain read of a memory cell output with high sensitivity and differential read with ease of design by detecting differentially a signal of a memory cell selected by a word selection signal and a signal of a dummy cell. CONSTITUTION:When the information of a memory cell M00 is ''0'', digit sense lines D0, D remain at high level, then a line DS is discharged toward a low level. When a set signal SET is impressed to a sense amplifier SA at the moment when the level reaches a proper level, the digit sense line DS is discharged to a low level in high speed. The digit sense lines D0, D are kept nearly to a high level voltage at that time. When the memory cell M00 is logical ''1'', the digit sense line D0, D go to a low level with the set signal SET impressed and the digit sense line DS is kept to a high level. Thus, the line D is kept to a voltage level in response to the information in high speed by the storage information of the memory cell M00.

Inventors

  • 👤 Kiyoo Ito
  • 👤 清男 伊藤
  • 👤 Yukinobu Chiba
  • 👤 千葉 幸悦
  • 👤 Katsuhiro Shimohigashi
  • 👤 下東 勝博

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 07:37
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34

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