semiconductor storage device

Abstract

Abstract PURPOSE:To attain a high degree of integration, a low level of power consumption and a high speed respectively for a semiconductor memory device, by using a data line of a memory array set close to an address decoder of a pair of memory arrays and a data line of the memory array set at the remote side of the address decoder as selection signal lines for data lines for memory arrays set at the remote and close sides of the address decoder respectively. CONSTITUTION:Pairs of memory arrays M-ARY1, M-ARY2 and M-ARY3, M- ARY4 are provided at the left and right sides of a column address decoder C- DCR, respectively. Then 128 pieces of memory cells and a dummy cell are provided to a pair of a parallel complementary data (bit) lines. A word line and a dummy word line are selected for one of pair memory arrays in accordance with an internal complementary address signal a8.

Inventors

• 👤 Katsuyuki Sato
• 👤 克之 佐藤

Bibliographic Details