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JPS59951A Expired / Lapsed JP ⏱️ 0.0 years remaining

2-layer wiring structure for chip carrier mounting substrate

Assignee: Fujitsu Ltd
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Filing: 1982-06-25
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Granted: —
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Expires: 2002-06-25
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Abstract

Abstract PURPOSE:To facilitate the exchange of a chip carrier by forming the first layer conductor of a thin film, and forming an insulator and the second layer conductor of thick films, thereby preventing the solder of the second layer conductor from cracking at the time of soldering the chip carrier. CONSTITUTION:The first layer conductor 2, an insulator 3 of thin film, an insulator 4 of thick film and the second layer conductor 5 of thick film are sequentially formed on the surface of a chip carrier placing substrate 1. A pad 7 for soldering the chip carrier is formed on the conductor 5. A thin film conductor 9 is formed on the surface of the through hole part 6 of the conductor 2 to extend on the insulator 3. The conductor 5 is connected via a conductor 9 to the through hole part 6. A solder resist 8 covers the surface of each formed layer except the pad 7.

Inventors

  • 👤 Kiyoshi Sato
  • 👤 清 佐藤
  • 👤 Minoru Terajima
  • 👤 寺島 稔
  • 👤 Masataka Koyama
  • 👤 小山 正孝
  • 👤 Kyoichi Rikitake
  • 👤 力武 恭一

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 13:15
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H10; H10W; H10W70/00; H10W70/60; H10W70/611; H10W70/67; H10W70/688; H05K3/40; H05K3/4007

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