Insulated gate field-effect transistor

Abstract

Abstract PURPOSE:To reduce ON resistance of the titled transistor by a method wherein a low density N type layer, a low density P type layer and a high density N type layer are laminated successively, a concavity having the depth reaching the low density N type layer is selectively formed, and a gate oxide film is formed on the surface of said concavity, thereby enabling to reduce a peak thereby lowering an ON-resistance. CONSTITUTION:The P type layer 23 and the N type layer 24 are formed on the high density N type silicon substrate 21 having a low density N type epitaxial layer. Then, a silicon nitride film 25 is grown, and it is removed by etching leaving the source region only. An etching is vertically performed on the silicon substrate 21 in such a manner that the P type layer 23 will be penetrated. After a photoresist has been removed, a gate oxide film 26 grown. The silicon nitride film 25 is selectively removed, and an aluminum alloy 27 is vapor-deposited on the whole surface. The aluminum alloy located at the stepping on the roughened part is removed by performing an etching.

Inventors

• 👤 Daisuke Ueda
• 👤 大助 上田
• 👤 Hiromitsu Takagi
• 👤 弘光 高木

Bibliographic Details