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JPS598197A Expired / Lapsed JP ⏱️ 0.0 years remaining

Test device of semiconductor memory

Assignee: Mitsubishi Electric Corp
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Filing: 1982-07-02
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Granted: —
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Expires: 2002-07-02
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Abstract

Abstract PURPOSE:To make it possible to test a semiconductor memory in the nibble mode, by providing a means which compares and discriminates contents of the first register, where the output from a high-speed buffer memory is stored, with those of the second register where reference data from a pattern generator is stored. CONSTITUTION:In the read operation of the nibble mode, data read out from a dynamic RAM 1 is transferred to the first register 8 through a very high-speed ECLRAM 7. Reference data 5 from a pattern generator 2 is transferred to the second register 9. These data are transferred to comparators 10a-10b simultaneously and are compared with each other, and a high level is outputted to an AND gate 11 if they coincide with each other, but a low level is outputted, if dissident, there. Thus, contents of defective bits are detected easily by checking the output of the gate 11. Output data in the nibble mode is compared and dis- criminated surely for high speed data transfer.

Inventors

  • 👤 Satoshi Takano
  • 👤 聡 高野

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 07:22
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/56

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