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JPS5979490A Expired / Lapsed JP ⏱️ 0.0 years remaining

Eprom circuit

Assignee: NEC Corp
•
Filing: 1982-10-27
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Granted: —
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Expires: 2002-10-27
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Abstract

Abstract PURPOSE:To obtain an EPROM circuit which can work at a low level of voltage by providing an oscillating circuit, a boosting circuit and a circuit which detects and controls the boosted voltage and supplying the boosted voltage to a decoder output buffer which works in a read mode and supplies an input to a control gate of a memory transistor (TR). CONSTITUTION:The figures show an example of a control circuit 3 which uses a CMOS device EPROM. This device EPROM consists of a p type MOSTRTP1, n type MOSTRs TN1, TN2 and TN3 and a memory TRTM, respectively. Both TRs TP1 and TN3 function as high resistances; while TRs TN1, TN2 and TM function as diodes having the threshold value of a TR. Then the potential of a point B becomes higher than that of a point A when the supply voltage VDX for an X decoder and a buffer is set higher than the voltage 2VTN+VTM as the threshold value TTM of TM as well as the threshold value TTN of TN2. Then the output of a differential amplifier S1 is inverted. This inverse signal controls an oscillator and a boosting circuit.

Inventors

  • 👤 Michitoku Kamatani
  • 👤 鎌谷 道徳

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-29 03:04
CPC Classifications
G; G11; G11C; G11C17/00

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