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JPS59761A Expired / Lapsed JP ⏱️ 0.0 years remaining

Picture processing system of plural processors

Assignee: Fujitsu Ltd
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Filing: 1982-06-28
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Granted: —
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Expires: 2002-06-28
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Abstract

Abstract PURPOSE:To improve the operating rate of a processor and to shorten the processing time, by sharing uniformly the number of coordinate to be calculated at the generation of a graph to each slave processor. CONSTITUTION:A multiplexer MPX switches a system control address SCA to a refresh memory RM and an access address of the slave processor SP. Processor modules PM1-PMn are programmed internally so that a continuous screen element is shared in order as to each raster on the screen and the operating processing such as the generation of a graph is executed at each of n-set of the screen elements. A master processor MP8 decodes a picture processing instruction inputted from an external circuit and gives a processing instruction in parallel to all the SPs. A system control circuit 13 generates a timing control signal such as supply of addresses to the RM under the control of the MP8.

Inventors

  • 👤 Shinichi Kuroki
  • 👤 伸一 黒木

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 20:20
CPC Classifications
—

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