Diagnostic system of logical circuit

Abstract

Abstract PURPOSE:To minimize the increase in diagnostic signal lines, by performing serially input/output of a device designated with an address input and its address at a shift register, and disconnecting a diagnostic circuit from a circuit to be diagnosed. CONSTITUTION:Addresses of a register 1 desired to be diagnosed, a memory 2 and a combined circuit 3 are inputted serially with a shift clock to a shift register 8. A device being the objective of diagnosis is selected with a selection signal from an address decoder 7 and the output is enabled. An output signal from the device to be diasnosed is loaded in parallel with a shift register 9 and outputted serially to an external circuit with the shift clock(scan mode). In setting an optional data to the specific device, data are inputted serially to the shift register 9 together with the shift clock (set mode).

Inventors

• 👤 Kiyoshi Sudo
• 👤 清 須藤
• 👤 Nobuyuki Baba
• 👤 信行 馬場
• 👤 Toshihiro Sakai
• 👤 酒井　利弘
• 👤 Hiroyuki Kaneda
• 👤 裕之 金田
• 👤 Toshiharu Oshima
• 👤 大島　俊春

Bibliographic Details