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JPS5966149A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Toshiba Corp
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Filing: 1982-10-08
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Granted: —
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Expires: 2002-10-08
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Abstract

Abstract PURPOSE:To improve the integration of multilayer wirings and an element by forming a connecting hole at the prescribed region of the second insulating film by an etching method faster than the etching speed of the first insulating film at the etching speed of the second insulating film, thereby preventing the disconnection of the second wiring conductor layer in the connecting hole. CONSTITUTION:A nitrided silicon film 5 is formed on the side of an aluminum wiring layer 3, a dioxidized silicon film 6 is accumulated by a plasma CVD method, a photoresist film 7 pattern is formed, and with the pattern as a mask a through hole 9 is formed at the film 6 by a reactive ion etching method using, for example, CF4/H2. Thereafter, the film 7 is removed, an aluminum film 8 is, for example, deposited and formed as the second wiring layer. The film 8 can be stopped to expose the part of the film 5 by etching by varying the condition of reactive ion etching method at the time of forming a through hole 9, thereby preventing the stepwise difference produced on the bottom of the through hole 9.

Inventors

  • 👤 Mitsunao Chiba
  • 👤 千葉 光直

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 20:46
CPC Classifications
—

Claims Analysis

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References Cited (Backward Citations)

JPS54142981A Cited

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