Accelerating and decelerating circuit

Abstract

Abstract PURPOSE:To simplify the circuit by processing a coarsely interpolated data from a coarse interpolating device as specified so as to reduce a circular arc path error. CONSTITUTION:The coarse interpolating device 301 generates coarse interpolating data DELTAXn, DELTAYn of each axis at one sampling and gives an input to accelerating and decelerating circuits 302X, 302Y. The newest data DELTAXn is stored in a buffer register #1 at each sampling, the content is transferred sequentially, and the content DELTAX0 of the register #n of the final stage is inputted to an adder ADD. And, the (n) is equal to tau/T, where tau is the time constant and T is the sampling time. The adder ADD operates DELTAXn-DELTAX0+St St, where St is the content of a register SUM and stores the result to an accumulator ACC. The content is divided into 1/n at a divider DIV. Thus, the circular arc path error is decreased and the circuit is simplified.

Inventors

• 👤 Ryoichiro Nozawa
• 👤 野沢　量一郎
• 👤 Hideaki Kawamura
• 👤 川村　英昭
• 👤 Takao Sasaki
• 👤 隆夫 佐々木

Bibliographic Details